1. Field of the Invention
The present invention relates to a delay circuit incorporating a capacitive element and, in particular, it relates to a delay circuit suitable for ring oscillators and to oscillators incorporating the delay circuit.
2. Description of Related Art
A delay circuit produces an output signal that is delayed with respect to the input signal. Many delay devices typically use Resistor-Capacitor (“RC”) circuits, where the delay is adjusted by varying a resistive and/or a capacitive load. In an integrated circuit using field effect transistors, such as MOS (Metal Oxide Semiconductor) transistors, the resistive and capacitive loads may be provided by transistors. Delay circuits are used in ring oscillators, which are important components of Phase-Locked Loop (“PLL”) circuits that have wide applications in the electronics world.
A ring oscillator is a circuit composed of a plurality of delay circuits that are coupled to form a ring. The ring oscillator achieves oscillation by inverting its input signal upon ring-traversal and delaying its output in response to the input. The amount of time required for an input signal to traverse the ring is determined by the sum of the individual delays of the delay circuits that form the ring. Thus, the period of oscillation of the ring oscillator can be controlled by varying the delays of its individual constituent delay circuits.
Ring oscillators are often used in phase-locked loop (“PLL”) circuits. In a phase-locked loop, an oscillator whose frequency and/or phase can be varied is synchronized in phase and/or frequency with a reference source. Therefore, the oscillator operates over a range of frequencies so that its frequency may be altered to match that of the reference source. The use of delay circuits in oscillators for PLLs is well known. See, for example, Ian A. Young “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, IEEE Journal Of Solid-State Circuits, Vol. 27, No. 11, November 1992; pp. 1599–1607 (“Young”); or Tsung-Hsien Lin, “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop”, IEEE Journal Solid-State Circuits, Vol. 36, No. 3, March 2001, pp. 424–431 (“Lin”), each of which is herein incorporated by reference in their entirety.
For conventional delay circuits, delay length is typically varied by changing the bias voltage of a MOS transistor in the circuit. Changing the bias voltage causes a variation in the current through the transistor, or the resistance of the transistor. However, the range of variation of the current through the transistor, or of the resistance of the transistor, is limited because of restrictions on the range of bias voltages. Therefore, in order to expand the range by which delay lengths can be varied, the capacitance value of capacitors in delay circuits is also varied.
Variation in the capacitance values is generally accomplished through the use of switching elements. This has the unfortunate consequence of introducing the parasitic capacitance of the switching elements into the delay circuit leading to an increase in the minimum value of delay length. As a result, the upper limit of the oscillation frequency of a ring oscillator incorporating such a delay circuit is reduced.
There is thus a need for delay circuits in which the delay length may be varied over a wide range without effects introduced by the parasitic capacitances of switching elements. The successful incorporation of such delay circuits into ring oscillators would also allow ring oscillators to operate over a greater range of frequencies.